In semiconductor devices, contacting schemes may be a large factor in balancing technology cost and scalability. For example, high density logic and bit cells may require efficient contacting schemes to utilize back end resources effectively. However, using too many layers used in contacts increases mask cost, and therefore increases wafer cost compared to semiconductor devices with fewer contact layers. A single additional mask level may increase cost by an amount in the order of millions of dollars. Therefore, each layer requiring a separate mask may increase fixed cost of a semiconductor device by a similar amount. Each technology generation may require a reduction in the sizes of standard cells. Corresponding to the required size reduction, local interconnects have been introduced for intra-cell routing to avoid congestion in the metal routing layers. An additional via layer may be used to provide an ohmic electrical connection between the local interconnect layers and the metal routing layers.
Reference is now made to FIG. 1, which is a plan view schematically illustrating a conventional semiconductor device including a plurality of finFETs. A conventional semiconductor device 100 may include finFETs 11-12 disposed on a substrate. Each finFET 11-12 may include a channel with source/drain regions on opposing sides of the channel. A gate stack 31-32 may be disposed on a top surface of the channel and may extend down sidewalls of the channel. Ones of trench contact regions 21-23 may be disposed on each of the source/drain regions. In some embodiments, trench contact regions 21-23 may each provide an ohmic electrical connection between multiple source/drain regions for finFETs containing multiple parallel fins. A metal routing layer may be separated from the finFETs in a vertical direction. The metal routing layer may include metal routes 41-42. For example, the metal routes 41-42 may include a power rail 41. The power rail 41 may not be above the trench contact regions 21-23 in a vertical direction. A first local interconnect 51 in a first local interconnect layer may extend from the trench contact region 21 to under the power rail 41. The first local interconnect layer may contact the trench contact layer and may not contact the metal routing layer. Thus, the first local interconnect 51 may contact trench contact region 21 and may not contact power rail 41. A via 61 may extend vertically from the first local interconnect 51 to contact the power rail 41. A trench contact region 22, a first local interconnect 52, and a via 63 may provide an ohmic electrical connection between a source/drain region and a metal route 42. Similarly, a second local interconnect 70 and a via 64 may provide an ohmic electrical connection between a gate stack 31-32 and another metal route 43.
Reference is now made to FIGS. 2A-2C, which are partial elevation views that are schematic in nature and illustrate select components of conventional semiconductor devices. As illustrated in FIG. 2A, a trench contact region 20, a first local interconnect 50, and a via 60 may provide an ohmic electrical connection between a source/drain region and a metal route 40. A second local interconnect 70, and a via 60 may provide an ohmic electrical connection between a gate stack 30 and a metal route 40. As illustrated in FIG. 2B, a first local interconnect 50 and respective trench contact regions 20 may provide an ohmic electrical connection between a plurality of source/drain regions. A via 60 may provide an ohmic electrical connection between the first local interconnect 50 and a metal route 40. As illustrated in FIG. 2C, a second local interconnect 70 may provide an ohmic electrical connection between a plurality of gate stacks 30. A via 60 may provide an ohmic electrical connection between the second local interconnect 70 and a metal route 40.